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Clock less Chip:


Clock less chips are electronic chips that are not using clock for timing signal.They

are implemented in asynchronous circuits. An asynchronous circuit is a circuit in which the

parts are largely autonomous. They are not governed by a clock circuit or global clock signal,

but instead need only wait for the signals that indicate completion of instructions and

operations. These signals are specified by simple data transfer protocols. This digital logic

design is contrasted with a synchronous circuit which operates according to clock timing


The term asynchronous logic is used to describe a variety of design styles, which use

different assumptions about circuit properties. These vary from the bundled delay model -

which uses 'conventional' data processing elements with completion indicated by a locally

generated delay model - to delay-insensitive design - where arbitrary delays through circuit

elements can be accommodated. The latter style tends to yield circuits which are larger and

slower than synchronous (or bundled data) implementations, but which are insensitive to

layout and parametric variations and are thus "correct by design."


[1] C.H.Van Berkel, Mark B. Josephs, and Steven M. Nowick, “Scanning the

Technology: Applications of Asynchronous Circuits”, proceedings of IEEE,

December 1998.

[2] Ivan E Sutherland and Jo Ebergen Scientific American , ”Computers without clocks”,

August 2002.

[3] David Geer published by IEEE Computer Society , ”Is it time for Clockless chips?”,

March 2005.

[4] Soha Hassoun, Yong-Bin Kim And Fabrizio Lombardi copublished by IEEE CS and

IEEE Guest Editor Introduction: “Clock less VLSI Systems”, November ñ December


[5] Claire Tristram from MIT Technology ,” It's Time for Clock less Chips” October 2001

and Old tricks for new chips Apr 19th 2001 From The Economist print edition.

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